NASA’s new HPE-built supercomputer will prepare for landing Artemis astronauts on the Moon – gpgmail


NASA and Hewlett Packard Enterprise (HPE) have teamed up to build a new supercomputer, which will serve NASA’s Ames Research Center in California and develop models and simulations of the landing process for Artemis Moon missions.

The new supercomputer is called ‘Aitken,’ named after American astronomer Robert Grant Aitken, and it can run simulations at up to 3.69 petaFLOPs of theoretical performance power. Aitken is custom-designed by HPE and NASA to work with the Ames modular data centre, which is a project it undertook starting in 2017 to massively reduce the amount of water and energy used in cooling its supercomputing hardware.

Aitken employs second generation Intel Xeon processors, Mellanox InfiniBand high-speed networking, and has 221 TB of memory on board for storage. It’s the result of four years of collaboration between NASA and HPE, and it will model different methods of entry, descent and landing for Moon-destined Artemis spacecraft, running simulations to determine possible outcomes and help determine the best, safest approach.

This isn’t the only collaboration between HPE and NASA: The enterprise computer maker built a new kind of supercomputer able to withstand the rigors of space for the agency, and sent it up to the ISS in 2017 for preparatory testing ahead of potential use on longer missions, including Mars. The two partners then opened that supercomputer for use in third-party experiments last year.

HPE also announced earlier this year that it was buying supercomputer company Cray for $1.3 billion. Cray is another long-time partner of NASA’s supercomputing efforts, dating back to the space agency’s establishment of a dedicated computational modelling division and the establishing of its Central Computing Facility at Ames Research Center.


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The renaissance of silicon will create industry giants – gpgmail


Every time we binge on Netflix or install a new internet-connected doorbell to our home, we’re adding to a tidal wave of data. In just 10 years, bandwidth consumption has increased 100 fold, and it will only grow as we layer on the demands of artificial intelligence, virtual reality, robotics and self-driving cars. According to Intel, a single robo car will generate 4 terabytes of data in 90 minutes of driving. That’s more than 3 billion times the amount of data people use chatting, watching videos and engaging in other internet pastimes over a similar period.

Tech companies have responded by building massive data centers full of servers. But growth in data consumption is outpacing even the most ambitious infrastructure build outs. The bottom line: We’re not going to meet the increasing demand for data processing by relying on the same technology that got us here.

The key to data processing is, of course, semiconductors, the transistor-filled chips that power today’s computing industry. For the last several decades, engineers have been able to squeeze more and more transistors onto smaller and smaller silicon wafers — an Intel chip today now squeezes more than 1 billion transistors on a millimeter-sized piece of silicon.

This trend is commonly known as Moore’s Law, for the Intel co-founder Gordon Moore and his famous 1965 observation that the number of transistors on a chip doubles every year (later revised to every two years), thereby doubling the speed and capability of computers.

This exponential growth of power on ever-smaller chips has reliably driven our technology for the past 50 years or so. But Moore’s Law is coming to an end, due to an even more immutable law: material physics. It simply isn’t possible to squeeze more transistors onto the tiny silicon wafers that make up today’s processors.

Compounding matters, the general-purpose chip architecture in wide use today, known as x86, which has brought us to this point, isn’t optimized for computing applications that are now becoming popular.

That means we need a new computing architecture. Or, more likely, multiple new computer architectures. In fact, I predict that over the next few years we will see a flowering of new silicon architectures and designs that are built and optimized for specialized functions, including data intensity, the performance needs of artificial intelligence and machine learning and the low-power needs of so-called edge computing devices.

The new architects

We’re already seeing the roots of these newly specialized architectures on several fronts. These include Graphic Processing Units from Nvidia, Field Programmable Gate Arrays from Xilinx and Altera (acquired by Intel), smart network interface cards from Mellanox (acquired by Nvidia) and a new category of programmable processor called a Data Processing Unit (DPU) from Fungible, a startup Mayfield invested in.  DPUs are purpose-built to run all data-intensive workloads (networking, security, storage) and Fungible combines it with a full-stack platform for cloud data centers that works alongside the old workhorse CPU.

These and other purpose-designed silicon will become the engines for one or more workload-specific applications — everything from security to smart doorbells to driverless cars to data centers. And there will be new players in the market to drive these innovations and adoptions. In fact, over the next five years, I believe we’ll see entirely new semiconductor leaders emerge as these services grow and their performance becomes more critical.

Let’s start with the computing powerhouses of our increasingly connected age: data centers.

More and more, storage and computing are being done at the edge; that means, closer to where our devices need them. These include things like the facial recognition software in our doorbells or in-cloud gaming that’s rendered on our VR goggles. Edge computing allows these and other processes to happen within 10 milliseconds or less, which makes them more work for end users.

I commend the entrepreneurs who are putting the silicon back into Silicon Valley.

With the current arithmetic computations of x86 CPU architecture, deploying data services at scale, or at larger volumes, can be a challenge. Driverless cars need massive, data-center-level agility and speed. You don’t want a car buffering when a pedestrian is in the crosswalk. As our workload infrastructure — and the needs of things like driverless cars — becomes ever more data-centric (storing, retrieving and moving large data sets across machines), it requires a new kind of microprocessor.

Another area that requires new processing architectures is artificial intelligence, both in training AI and running inference (the process AI uses to infer things about data, like a smart doorbell recognizing the difference between an in-law and an intruder). Graphic Processing Units (GPUs), which were originally developed to handle gaming, have proven faster and more efficient at AI training and inference than traditional CPUs.

But in order to process AI workloads (both training and inference), for image classification, object detection, facial recognition and driverless cars, we will need specialized AI processors. The math needed to run these algorithms requires vector processing and floating-point computations at dramatically higher performance than general purpose CPUs provide.

Several startups are working on AI-specific chips, including SambaNova, Graphcore and Habana Labs. These companies have built new AI-specific chips for machine intelligence. They lower the cost of accelerating AI applications and dramatically increase performance. Conveniently, they also provide a software platform for use with their hardware. Of course, the big AI players like Google (with its custom Tensor Processing Unit chips) and Amazon (which has created an AI chip for its Echo smart speaker) are also creating their own architectures.

Finally, we have our proliferation of connected gadgets, also known as the Internet of Things (IoT). Many of our personal and home tools (such as thermostats, smoke detectors, toothbrushes and toasters) operate on ultra-low power.

The ARM processor, which is a family of CPUs, will be tasked for these roles. That’s because gadgets do not require computing complexity or a lot of power. The ARM architecture is perfectly designed for them. It’s made to handle smaller number of computing instructions, can operate at higher speeds (churning through many millions of instructions per second) and do it at a fraction of the power required for performing complex instructions. I even predict that ARM-based server microprocessors will finally become a reality in cloud data centers.

So with all the new work being done in silicon, we seem to be finally getting back to our original roots. I commend the entrepreneurs who are putting the silicon back into Silicon Valley. And I predict they will create new semiconductor giants.


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Nvidia Unveils Conversational AI Tech for Smarter Bots


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Now that nearly every possible mobile device and appliance has either adopted or at least experimented with voice control, conversational AI is quickly becoming the new frontier. Instead of handling one query and providing one response or action, conversational AI aims to provide a realtime interactive system that can span multiple questions, answers, and comments. While the fundamental building blocks of conversational AI, like BERT and RoBERTa for language modeling, are similar to those for one-shot speech recognition, the concept comes with additional performance requirements for training, inferencing, and model size. Today, Nvidia released and open-sourced three technologies designed to address those issues.

Faster Training of BERT

Nvidia DGX SuperPODWhile in many cases it’s possible to use a pre-trained language model for new tasks with just some tuning, for optimal performance in a particular context re-training is a necessity. Nvidia has demonstrated that it can now train BERT (Google’s reference language model) in under an hour on a DGX SuperPOD consisting of 1,472 Tesla V100-SXM3-32GB GPUs, 92 DGX-2H servers, and 10 Mellanox Infiniband per node. No, I don’t want to even try and estimate what the per-hour rental is for one of those. But since models like this have typically taken days to train even on high-end GPU clusters, this will definitely help time to market for companies who can afford the cost.

Faster Language Model Inferencing

For natural conversations, the industry benchmark is 10ms response time. Understanding the query and coming up with a suggested reply is just one part of the process, so it needs to take less than 10ms. By optimizing BERT using TensorRT 5.1, Nvidia has it inferencing in 2.2ms on an Nvidia T4. What’s cool is that a T4 is actually within the reach of just about any serious project. I used them in the Google Compute Cloud for my text generation system. A 4-vCPU virtual server with a T4 rented for just over $1/hour when I did the project.

Support for Even Larger Models

Faster inferencing is needed for conversational AIOne of the Achilles’ Heels of neural networks is the requirement that all of the model’s parameters (including a large number of weights) need to be in memory at once. That limits the complexity of the model that can be trained on a GPU to the size of its RAM. In my case, for example, my desktop Nvidia GTX 1080SEEAMAZON_ET_135 See Amazon ET commerce can only train models that fit in its 8GB. I can train larger models on my CPU, which has more RAM, but it takes a lot longer. The full GPT-2 language model has 1.5 billion parameters, for example, and an extended version has 8.3 billion.

Nvidia, though, has come up with a way to allow multiple GPUs to work on the language modeling task in parallel. Like with the other announcements today, they have open-sourced the code to make it happen. I’ll be really curious if the technique is specific to language models or can be applied to allow multiple-GPU training for other classes of neural networks.

Along with these developments and releasing the code on GitHub, Nvidia announced that they will be partnering with Microsoft to improve Bing search results, as well as with Clinc on voice agents, Passage AI on chatbots, and RecordSure on conversational analytics.

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