Porsche invests in ‘low visibility’ sensor startup TriEye – gpgmail


Porsche’s venture arm has acquired a minority stake in TriEye, an Israeli startup that’s working on a sensor technology to help vehicle driver-assistance and self-driving systems see better in poor weather conditions like dust, fog and rain.

The strategic investment is part of a Series A financing round that has been expanded to $19 million. The round was initially led by Intel Capital and Israeli venture fund Grove Ventures. Porsche has held shares in Grove Ventures since 2017.

TriEye has raised $22 million to date. Terms of Porsche’s investment were not disclosed.

The additional funding will be used for ongoing product development, operations and hiring talent, according to TriEye.

The advanced driver-assistance systems found in most new vehicles today typically rely on a combination of cameras and radar to “see.” Autonomous vehicle systems, which are being developed and tested by dozens of companies such as Argo AI, Aptiv, Aurora, Cruise and Waymo, have a more robust suite of sensors that include light detection and ranging radar (lidar) along with cameras and ultrasonic sensors.

For either of these systems to function properly, they need to be able to see in all conditions. This pursuit of sensor technology has sparked a boom in startups hoping to tap into demand from automakers and companies working on self-driving car systems.

TriEye is one of them. The premise of TriEye is to solve the low visibility problem created by poor weather conditions. The startup’s co-founders argue that fusing existing sensors such as radar, lidar and standard cameras don’t solve this problem.

TriEye, which was founded in 2017, believes the answer is through short-wave infrared (SWIR) sensors. The startup said it has developed an HD SWIR camera that is a smaller size, higher resolution and cheaper than other technologies. The camera is due to launch in 2020.

The technology is based on advanced nano-photonics research by Uriel Levy, a TriEye co-founder and CTO who is also a professor at the Hebrew University of Jerusalem.

The company says its secret sauce is its “unique” semiconductor design that will make it possible to manufacture SWIR HD cameras at a “fraction of their current cost.”

TriEye’s technology was apparently good enough to get Porsche’s attention.

Michael Steiner, a Porsche AG board member focused on R&D, said the technology was promising, as was the team, which is comprised of people with expertise in deep learning, nano-photonics and semiconductor components.

“We see great potential in this sensor technology that paves the way for the next generation of driver assistance systems and autonomous driving functions,” Steiner said in a statement. “SWIR can be a key element: it offers enhanced safety at a competitive price.”


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Y Combinator-backed Holy Grail is using machine learning to build better batteries – gpgmail


For a long, long time, renewable energy proponents have considered advancements in battery technology to be the holy grail of the industry.

Advancements in energy storage has been among the hardest to achieve economically thanks to the incredibly tricky chemistry that’s involved in storing power.

Now, one company that’s launching from Y Combinator believes it has found the key to making batteries better. The company is called Holy Grail and it’s launching in the accelerator’s latest cohort.

With an executive team that initially included Nuno Pereira, David Pervan, and Martin Hansen, Holy Grail is trying to bring the techniques of the fabless semiconductor industry to the world of batteries.

The company’s founders believe that the only way to improve battery functionality is to take a systems approach to understanding how different anodes and cathodes will work together. It sounds simple, but Pereira says that the computational power hadn’t existed to take into account all of the variables that go along with introducing a new chemical to the battery mix.

“You can’t fix a battery with just a component,” Pereira says. “All of the batteries that were created and failed in the past. They create an anode, but they don’t have a chemical that works with the cathode or the electrolyte.”

For Pereira, the creation of Holy Grail is the latest step on a long road of experimentation with mechanical and chemical engineering. “As a kid I was more interested in mechanical engineering and building stuff,” he says. But as he began tinkering with cars and became fascinated with mobility, he realized that batteries were the innovation that gave the world its charge.

In 2017 Pereira founded a company called 10Xbattery, which was making high-density lithium batteries. That company, launching with what Pereira saw as a better chemistry, encapsulated the industry’s problem at large — the lack

So, with the help of a now-departed co-founder, Pereira founded Holy Grail. “He essentially told me, ‘Do you want to take a step back and see if there’s a better way to do this?’” said Pereira.

The company pitches itself as science fiction coming from the future, but it relies on a combination of what are now fairly standard (at least in the research community) tools. Holy Grail’s pitch is that it can automate much of the research and development process to create new batteries that are optimized to the specifications of end customers.

“It’s hard for a human to do the experiments that you need and to analyze multidimensional data,” says Pereira. “There are some companies that only do the machine-learning part and the computational science part and sell the results to companies. The problem is that there’s a disconnection between experimental reality and the simulations.”

Using computer modeling, chemical engineering and automated manufacturing, Holy Grail pitches a system that can get real test batteries into the hands of end customers in the mobility, electronics, and utility industries orders of magnitude more quickly than traditional research and development shops.

Currently the system that Holy Grail has built out can make 700 batteries per day. The company intends to  build a pilot plant that will make batteries for electronics and drones. For automotive and energy companies, Holy Grail says it will partner with existing battery manufacturers that can support the kind of high-throughput manufacturing big orders will require.

Think of it like bringing the fabless chip design technologies and business models to the battery industry, says Pereira.

Holy Grail already has $14 million in letters of intent with potential customers, according to Pereira and is expecting to close additional financing as it exits Y Combinator.

To date the company has been backed by the London-based early stage investment firm Deep Science Ventures, where Pereira worked as an entrepreneur in residence.

Ultimately, the company sees its technology being applied far beyond batteries as a new platform for materials science discoveries broadly. For now, though the focus is on batteries.

“For the low volume we sell direct,” says Pereira. “While on high volume production, we will implement a pilot line through the system… we are able to do the research engineering with the small ones and test the big ones. In our case when we have a cell that works, it’s not something that works in a lab it’s something that works in the final cell.”


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How Are Process Nodes Defined?


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We talk a lot about process nodes at ExtremeTech, but we don’t often refer back to what a process node technically is. With Intel’s 10nm node moving towards production, I’ve noticed an uptick in conversations around this issue and confusion about whether TSMC and Samsung possess a manufacturing advantage over Intel (and, if they do, how large an advantage they possess).

Process nodes are typically named with a number followed by the abbreviation for nanometer: 32nm, 22nm, 14nm, etc. There is no fixed, objective relationship between any feature of the CPUSEEAMAZON_ET_135 See Amazon ET commerce and the name of the node. This was not always the case. From roughly the 1960s through the end of the 1990s, nodes were named based on their gate lengths. This chart from IEEE shows the relationship:

lithot1

For a long time, gate length (the length of the transistor gate) and half-pitch (half the distance between two identical features on a chip) matched the process node name, but the last time this was true was 1997. The half-pitch continued to match the node name for several generations but is no longer related to it in any practical sense. In fact, it’s been a very long time since our geometric scaling of processor nodes actually matched with what the curve would look like if we’d been able to continue actually shrinking feature sizes.

2010-ITRS-Summary

Well below 1nm before 2015? Pleasant fantasy.

If we’d hit the geometric scaling requirements to keep node names and actual feature sizes synchronized, we’d have plunged below 1nm manufacturing six years ago. The numbers that we use to signify each new node are just numbers that companies pick. Back in 2010, the ITRS (more on them in a moment) referred to the technology chum bucket dumped in at every node as enabling “equivalent scaling.” As we approach the end of the nanometer scale, companies may begin referring to angstroms instead of nanometers, or we may simply start using decimal points. When I started work in this industry it was much more common to see journalists refer to process nodes in microns instead of nanometers — 0.18-micron or 0.13-micron, for example, instead of 180nm or 130nm.

How the Market Fragmented

Semiconductor manufacturing involves tremendous capital expenditure and a great deal of long-term research. The average length of time between when a new technological approach is introduced in a paper and when it hits widescale commercial manufacturing is on the order of 10-15 years. Decades ago, the semiconductor industry recognized that it would be to everyone’s advantage if a general roadmap existed for node introductions and the feature sizes those nodes would target. This would allow for the broad, simultaneous development of all the pieces of the puzzle required to bring a new node to market. For many years, the ITRS — the International Technology Roadmap for Semiconductors — published a general roadmap for the industry. These roadmaps stretched over 15 years and set general targets for the semiconductor market.

SemiconductorRoadmap

Image by Wikipedia

The ITRS was published from 1998-2015. From 2013-2014, the ITRS reorganized into the ITRS 2.0, but soon recognized that the scope of its mandate — namely, to provide “the main reference into the future for university, consortia, and industry researchers to stimulate innovation in various areas of technology” required the organization to drastically expand its reach and coverage. The ITRS was retired and a new organization was formed called IRDS — International Roadmap for Devices and Systems — with a much larger mandate, covering a wider set of technologies.

This shift in scope and focus mirrors what’s been happening across the foundry industry. The reason we stopped tying gate length or half-pitch to node size is that they either stopped scaling or began scaling much more slowly. As an alternative, companies have integrated various new technologies and manufacturing approaches to allow for continued node scaling. At 40/45nm, companies like GF and TSMC introduced immersion lithography. Double-patterning was introduced at 32nm. Gate-last manufacturing was a feature of 28nm. FinFETs were introduced by Intel at 22nm and the rest of the industry at the 14/16nm node.

Companies sometimes introduce features and capabilities at different times. AMD and TSMC introduced immersion lithography at 40/45nm, but Intel waited until 32nm to use that technique, opting to roll out double-patterning first. GlobalFoundries and TSMC began using double-patterning more at 32/28nm. TSMC used gate-last construction at 28nm, while Samsung and GF used gate-first technology. But as progress has gotten slower, we’ve seen companies lean more heavily on marketing, with a greater array of defined “nodes.” Instead of waterfalling over a fairly large numerical space (90, 65, 45) companies like Samsung are launching nodes that are right on top of each other, numerically speaking:

I think you can argue that this product strategy isn’t very clear, because there’s no way to tell which process nodes are evolved variants of earlier nodes unless you have the chart handy. But a lot of the explosion in node names is basically marketing.

Why Do People Claim Intel 7nm and TSMC/Samsung 10nm Are Equivalent?

While node names are not tied to any specific feature size, and some features have stopped scaling, semiconductor manufacturers are still finding ways to improve on key metrics. The chart below is drawn from WikiChip, but it combines the known feature sizes for Intel’s 10nm node with the known feature sizes for TSMC’s and Samsung’s 7nm node. As you can see, they’re very similar:

Intel-10-Foundry-7

Image by ET, compiled from data at WikiChip

The delta 14nm / delta 10nm column shows how much each company scaled a particular feature down from its previous node. Intel and Samsung have a tighter minimum metal pitch than TSMC does, but TSMC’s high-density SRAM cells are smaller than Intel’s, likely reflecting the needs of different customers at the Taiwanese foundry. Samsung’s cells, meanwhile, are even smaller than TSMC’s. Overall, however, Intel’s 10nm process hits many of the key metrics as what both TSMC and Samsung are calling 7nm.

Individual chips may still have features that depart from these sizes due to particular design goals. The information manufacturers provide on these numbers are for a typical expected implementation on a given node, not necessarily an exact match for any specific chip.

There have been questions about how closely Intel’s 10nm+ process (used for Ice Lake) reflects these figures (which I believe were published for Cannon Lake). It’s true that the expect specifications for Intel’s 10nm node may have changed slightly, but 14nm+ was an adjustment from 14nm as well. Intel has stated that it is still targeting a 2.7x scaling factor for 10nm relative to 14nm, so we’ll hold off on any speculation about how 10nm+ may be slightly different.

Pulling It All Together

The best way to understand the meaning of a new process node is to think of it as an umbrella term. When a foundry talks about rolling out a new process node, what they are saying boils down to this:

“We have created a new manufacturing process with smaller features and tighter tolerances. In order to achieve this goal, we have integrated new manufacturing technologies. We refer to this set of new manufacturing technologies as a process node because we want an umbrella term that allows us to capture the idea of progress and improved capability.”

Any additional questions on the topic? Drop them below and I’ll answer them.

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